IBM's research into the evaluation of coupling noise and signal integrity has enhanced the advances in silicon CMOS technologies. But, both wire density and circuit speed have increased to the point that signal integrity, in particular the coupling noise of the on-chip interconnect has become a significant issue with respect to chip functionality, performance and reliability. The IBM research has been illustrated in the patent literature, illustrated by U.S. Pat. No. 6,342,832, issued Jan. 29, 2002, entitled: System and Method for Reducing Calculation Complexity of Lossy, Frequency-Dependent Transmission-Line Computation with Allan Dansky, Alina Deutsch, Gerard Kopcsay, Phillip Restle, and Howard Smith, named inventors; U.S. Pat. No. 6,418,401, issued Jul. 9, 2002, entitled: Efficient Method of Modeling Three-Dimensional Interconnect Structures for Frequency-Dependent Crosstalk Simulation, naming Allan Dansky, Alina Deutsch, Gerard Kopcsay, Phillip Restle, and Howard Smith, inventors; U.S. Pat. No. 6,086,238. Jul. 11, 2000, entitled:. Method and System for Shape Processing within an Integrated Circuit Layout for Parasitic Capacitance Estimation, naming Sharad Mehrotra, Paul Gerard Villarrubia, and David James Widiger, inventors; and U.S. Pat. No. 6,523,149, issued Feb. 18, 2003, based upon U.S. Ser. No. patent application No. 09/666,272, filed Sep. 21, 2000, entitled: METHOD AND SYSTEM TO IMPROVE NOISE ANALYSIS PERFORMANCE OF ELECTRICAL CIRCUITS, naming David Widiger, Mark Wenning, and Sharad Mehrotra, as inventors.
As background for the discussion of our improvements, we refer to the following evaluation methodologies which have been developed:
Referring to the above evaluations, we note that (1) shows a verification methodology that has been developed to assure appropriate noise levels are maintained within apportioned limits to allow evaluation of all global level nets within a chip hierarchy. Such techniques employee coupled RC extraction due to the premise that capacitive coupling is the primary noise injection mechanism. However, we have found that there exists conditions where some nets could experience both capacitive and inductive coupling or inductive coupling only. There are approximate conditions in which the RC modeling of the coupled noise yields greater than 25% error in the amplitude calculation conditions set forth above as (1), (2),(3) and (4).Rwire_perp<30 ohms/mm  (1)Rwire_vict<60 ohms/mm  (2)Rwire_perp*Lc/2*Zo<1.5  (3)Zdrv<1.5*Zo  (4)
These conditions readily exist on high performance ASICs and microprocessor designs. It should be pointed out that all conditions, (1-4), should exist to experience inductive behavior. However in cases where one of the conditions was “significantly” satisfied the other condition need not be satisfied in order to experience inductive behavior. In Actual practice the error can be significantly higher when considering net topology. Hardware failures as well as research in this area have deduced the presence of such an effect and the limitation of current signal integrity practices which employee only RC models.